This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-301306, filed Sep. 29, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and a semiconductor device mounting interconnection board and more particularly to an Si (silicon) semiconductor chip and an interconnection board formed of Si.
2. Description of the Related Art
When a semiconductor device is mounted on a resin-series mounting board, it is necessary to make a design so as to prevent breakage of the electrical connection between a semiconductor chip and the mounting board by stress due to a temperature change, since Si, forming the semiconductor chip, has a small thermal expansion coefficient (5 ppm) and the resin used for forming the mounting board has a large thermal expansion coefficient (17 ppm in the case of BT resin, for example). The above problem becomes more significant as the designed density of elements becomes higher and the elements are further miniaturized, and particularly, the problem becomes serious in CSP (Chip Scale Package or Chip Size Package) using the flip chip technique.
For example, in the technique disclosed in U.S. Pat. No. 5,148,266 and Jpn. Pat. Appln. KOKAI Publication No. 11-284099, connection with the semiconductor chip is made by use of a flexible beam lead or gold wire and elastomer is used to make it difficult to transmit stress from the semiconductor chip to a solder ball, which is a connection terminal for connection with the mounting board.
FIG. 1 is a cross sectional view showing the package structure disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-284099. A semiconductor chip 1 is adhered to an organic insulating tape 14 via an elastomer layer 6 and interconnections of the semiconductor chip 1 and interconnections 15 on the organic insulating tape 14 are respectively connected via bonding wires 9. The bonding wires 9 are covered with a resin layer 13. Further, BGA balls 4 are formed on the interconnections 15 on the organic insulating tape 14.
With the above structure, since the BGA balls 4 which are formed on the undersurface of the organic insulating tape 14 and used as external connection terminals are separated from the semiconductor chip 1 by the elastomer layer 6, the stress due to a difference in the thermal expansion between the semiconductor chip 1 and the mounting board can be alleviated.
However, with the above structure, since a large difference in thermal expansion exists between the semiconductor chip 1 and the organic insulating tape 14, the package will be warped even though the elastomer layer 6 is disposed therebetween. Since the uniform height of each of the external connection terminals (BGA balls 4) is more strictly required and the connection strength thereof becomes lower as the pitch therebetween becomes smaller, it is necessary to further reduce the stress applied to the external connection terminals. Therefore, with the package of the above structure, at present, it is difficult to cope with a connection pitch smaller than 0.5 mm, for example.
The above problem occurs in exactly the same manner in the technique disclosed in other known publications similar to the technique disclosed in U.S. Pat. No. 5,148,266 and a technique for providing a connection structure effective for a connection pitch smaller than 0.5 mm has not yet been developed.
According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor chip; an external connection terminal formed on a circuit forming surface side of the semiconductor chip; an outer moat formed in a portion of the semiconductor chip which surrounds the external connection terminal and penetrating therethrough in a doughnut form; a first interconnection formed on a portion of the semiconductor chip which lie on the circuit forming surface side and is surrounded by the outer moat and electrically connected to the external connection terminal; a second interconnection formed on the circuit forming surface side of the semiconductor chip outside the outer moat and electrically connected to an internal circuit; and a conductor which electrically connects the first and second interconnections to each other, the conductor having at least one bent portion.
According to another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor chip; an external connection terminal formed on a rear surface side of the semiconductor chip which is opposite to a circuit forming surface side thereof; an outer moat formed in a portion of the semiconductor chip which surrounds the external connection terminal and penetrating therethrough in a doughnut form; a first interconnection formed on a portion of the semiconductor chip which lie on the circuit forming surface side and is surrounded by the outer moat and electrically connected to the external connection terminal via a penetration hole formed in the semiconductor chip; a second interconnection formed on the circuit forming surface side of the semiconductor chip outside the outer moat and electrically connected to an internal circuit; and a conductor which electrically connects the first and second interconnections to each other, the conductor having at least one bent portion.
According to still another aspect of the present invention, there is provided a semiconductor device comprising an interconnection board; a semiconductor body adhered to the interconnection board by use of an elastomer; an internal connection terminal formed in an adhering potion between the semiconductor body and the interconnection board and electrically connected to an internal circuit of the semiconductor body; an external connection terminal formed on a rear surface side of the interconnection board which lies opposite to a semiconductor body mounting surface thereof; an outer moat formed in a portion of the interconnection board which surrounds the external connection terminal and penetrating therethrough in a doughnut form; a first interconnection formed on a portion of the interconnection board which is surrounded by the outer moat and electrically connected to the external connection terminal; a second interconnection formed on a portion of the interconnection board which lies outside the outer moat and electrically connected to the internal connection terminal; and a conductor which electrically connects the first and second interconnections to each other, the conductor having at least one bent portion.
According to another aspect of the present invention, there is provided a semiconductor device mounting interconnection board comprising a board main body; an external connection terminal formed on one-surface side of the board main body; an outer moat formed in a portion of the board main body which surrounds the external connection terminal and penetrating therethrough in a doughnut form; a first interconnection formed on a portion of the board main body which is surrounded by the outer moat and electrically connected to the external connection terminal; a second interconnection formed on a portion of the board main body which lies outside the outer moat; and a conductor which electrically connects the first and second interconnections to each other, the conductor having at least one bent portion; wherein a semiconductor chip is mounted on another surface of the board main body which is different from the one-surface of the board main body.